Akademik Veri Yönetim Sistemi
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, cilt.113, sa.2, ss.211-221, 2022 (SCI-Expanded)
This paper presents design of a 6-bit two channel time interleaved (TI) ADC in TSMC 180 nm CMOS technology. Threshold Inverter Quantization (TIQ) based flash ADC cores are used in both TI channels. In this design, speed performance and low power properties are focused design goals. For this purpose, standart CMOS logic gates are preferred as much as possible together with the so-called TIQ comparator structure, which is also a CMOS logic for the analog part of the flash ADC cores. The aspect ratio of the MOS transistors used in the design are choosen carefully to be able to achieve high performance goals as much as possible. The main contribution of this study is to employ the TIQ technique for the second time in TI ADC architectures. The first time realization was also presented by the same authors in ELECO 2018 conference. However, resolution is now increased to 6-bit and more professional design tool is used. Moreover, important design updates became necessary in some of the design blocks. According to simulation results, the proposed TI ADC has the sampling rate of 8 Gs/s. The simulation results also include + 0.148/- 0.574 LSB of INL and + 0.195/- 0.163 LSB of DNL values obtained from DC results. The DNL and INL calculations were also obtained using transient analysis results. While the power consumption of a single flash ADC core at 4 Gs/s is 69.82 mW, the power consumption of the complete two-channel TI ADC is 166.5 mW at 8 Gs/s sampling rate. The fabrication of the proposed ADC is projected as a future work.