Field programmable gate arrays implementation of two-point non-uniformity correction and bad pixel replacement algorithms

Njuguna J. C., Alabay E., ÇELEBİ A., Celebi A., Gullu M. K.

2021 International Conference on INnovations in Intelligent SysTems and Applications, INISTA 2021, Kocaeli, Türkiye, 25 - 27 Ağustos 2021 identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Doi Numarası: 10.1109/inista52262.2021.9548499
  • Basıldığı Şehir: Kocaeli
  • Basıldığı Ülke: Türkiye
  • Anahtar Kelimeler: Bad pixel replacement, Fixed pattern noise, FPGA, HLS, IRFPA, Two-point non-uniformity correction
  • Kocaeli Üniversitesi Adresli: Evet

Özet

In this paper, the hardware architecture for two-point non-uniformity correction (TPNUC) and bad pixel replacement (BPR) algorithms are presented based on field-programmable gate arrays (FPGA) for infrared focal plane arrays (IRFPA). An efficient hardware architecture modeled using C++ in the High-Level Synthesis (HLS) tool is presented. The design is tested on an FPGA fabricated at a 16 nm technology node. The design achieves a maximum frequency of 300 MHz and one pixel per clock. A thermal camera development platform (FullScale USB3A) with a resolution of 640×480 is used as the source for the raw video. The simulation results from MATLAB and FPGA posed close similarities.