Design and Implementation of 256-Point Radix-4 100 Gbit/s FFT Algorithm into FPGA for High-Speed Applications

Creative Commons License

Polat G., ÖZTÜRK S. , Yakut M.

ETRI JOURNAL, vol.37, no.4, pp.667-676, 2015 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 37 Issue: 4
  • Publication Date: 2015
  • Doi Number: 10.4218/etrij.15.0114.0678
  • Title of Journal : ETRI JOURNAL
  • Page Numbers: pp.667-676


The third-party FFT IP cores available in today's markets do not provide the desired speed demands for optical communication. This study deals with the design and implementation of a 256-point Radix-4 100 Gbit/s FFT, where computational steps are reconsidered and optimized for high-speed applications, such as radar and fiber optics. Alternative methods for FFT implementation are investigated and Radix-4 is decided to be the optimal solution for our fully parallel FPGA application. The algorithms that we will implement during the development phase are to be tested on a Xilinx Virtex-6 FPGA platform. The proposed FFT core has a fully parallel architecture with a latency of nine clocks, and the target clock rate is 312.5 MHz.