CMOS differential cross-coupled LC oscillators are widely used due to their superior phase noise performance. Even though the number of circuit elements is small, the design process is not trivial due to the complicated trade-off between the phase noise and power consumption. Conventionally, cross-coupled oscillators can be constructed by using only PMOS or only NMOS devices or using both (CMOS). The topology selection is mostly based on either theoretical calculations or experimental (measurement/simulation) results on specific solution points reported in the literature; however, there is no comprehensive analysis on comparison of these topologies in the literature. Also, there are several efforts on improving the phase noise response such as conventional tail noise filtering (using a tail capacitor or LC filter) and sinusoidal tail shaping. Yet, the cost-performance effectiveness of such techniques has not been well-discussed in the literature. In this study, performances of different differential cross-coupled LC oscillators are examined using a parasitic-aware multi-objective RF circuit synthesis tool. PMOS, NMOS, and CMOS types of oscillators were synthesized and performances of those circuits were thoroughly demonstrated. The synthesis results were validated by performing post-layout simulations for different solutions located on the Pareto optimal front (POF). To observe the effect of the other layout parasitics, the CMOS oscillator was also optimized including a parasitic netlist of a drawn layout. The effect of using LC tank with centre-tapped inductor on oscillator performance was also investigated. Furthermore, effectiveness of several phase noise reduction techniques; tail capacitor filtering, tail LC filtering, and sinusoidal noise shaping were demonstrated and discussed in detail.