Implementation and Optimization of LeNet-5 Model for Handwritten Digits Recognition on FPGAs using Brevitas and FINN

Njuguna J. C., Celebi A. T., ÇELEBİ A.

2023 Innovations in Intelligent Systems and Applications Conference, ASYU 2023, Sivas, Türkiye, 11 - 13 Ekim 2023 identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Doi Numarası: 10.1109/asyu58738.2023.10296630
  • Basıldığı Şehir: Sivas
  • Basıldığı Ülke: Türkiye
  • Anahtar Kelimeler: BNN, Brevitas, CNN, FINN, FPGA, Hardware Acceleration, HLS, LeNet-5, Quantization, RISCV
  • Kocaeli Üniversitesi Adresli: Evet

Özet

Handwritten digit recognition using deep learning models is an active area of research with wide-ranging applications. However, the high computational requirements of these models limit their deployment on resource-constrained devices. To address this challenge, we propose an optimized implementation of the LeNet-5 model for handwritten digit recognition on FPGAs using the Brevitas and FINN frameworks. We trained the model on the MNIST dataset and quantized it to reduce its memory footprint and improve inference performance. We then used FINN to generate hardware operators and RTL code, which were synthesized for an EFINIX FPGA. Additionally, we used a RISC-V processor and custom HLS VDMAs to interface with the FPGA and enable image loading and result display through GUI. Our approach achieved a classification accuracy of 96.64% on the test set, while consuming significantly lower power than CPU and GPU implementations. Our methodology demonstrates the potential of leveraging FPGA hardware acceleration to enable efficient deployment of deep learning models on resource-constrained devices.