ICENTE 2021, Konya, Turkey, 18 - 21 November 2021, pp.1-5
This paper presents design steps of a 6-bit two-channel time-interleaved (TI) ADC in 0.25µm Si-Ge HBT BiCMOS technology. Two 6-bit flash ADC cores are used in both time-interleaved channels. In digital parts of the design, standard CMOS logic gates are preferred since a low power consumption value is one of the main targets of this work. Transistor sizes are selected carefully to be able to obtain as high as possible speed performance, which is another main goal of this study. The main core design blocks of the complete TI ADC are sample/hold circuit, 6-Bit Flash ADC, a 6-bit 2x1 digital multiplexer, and a control pulse generator. BiCMOS analog comparator architecture is preferred in the analog part of flash ADC since BiCMOS technology combines the advantages of CMOS and Bipolar technologies. The power consumption value is 653 mW under a single DC power supply voltage of 3.3V. The simulation results include 7Gs/s sampling rate, 0,174 LSB of INL and 0,113 LSB of DNL values. The simulation results are compared to similar works in the literature. For the time being, the complete design is realized using Cadence IC design platform in schematic level only. However, the physical layout design and post-layout simulation steps are ongoing research of us.