Efficient Hardware Implementations of Low Bit Depth Motion Estimation Algorithms

ÇELEBİ A., URHAN O., Hamzaoglu I., ERTÜRK S.

IEEE SIGNAL PROCESSING LETTERS, vol.16, no.6, pp.513-516, 2009 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 16 Issue: 6
  • Publication Date: 2009
  • Doi Number: 10.1109/lsp.2009.2017222
  • Journal Name: IEEE SIGNAL PROCESSING LETTERS
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Page Numbers: pp.513-516
  • Kocaeli University Affiliated: Yes

Abstract

In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures.