Efficient Hardware Implementations of Low Bit Depth Motion Estimation Algorithms

ÇELEBİ A. , URHAN O. , Hamzaoglu I., ERTÜRK S.

IEEE SIGNAL PROCESSING LETTERS, cilt.16, ss.513-516, 2009 (SCI İndekslerine Giren Dergi) identifier identifier

  • Cilt numarası: 16 Konu: 6
  • Basım Tarihi: 2009
  • Doi Numarası: 10.1109/lsp.2009.2017222
  • Sayfa Sayıları: ss.513-516


In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures.