Motivation of analog circuit automation tools has focused on improving the efficiency, where solving of a highly nonlinear design problem takes considerably long time even if the process is fully automated. One of the problems of the circuit sizing tools is inaccurate performance evaluations, where operation regions of transistors are roughly estimated with simplified models. Typically, inversion coefficient (IC) is commonly used to determine the actual operation region of a transistor, which gives detailed and accurate information about the whole saturation region (weak, moderate, and strong inversion). Co-optimization IC of transistors considering the figure of merit (FOM) for a given problem can canalize the optimizer to find circuits biased properly and enhance the efficiency of the synthesis tools. In this study, an IC optimization based analog/RF circuit sizing approach is proposed, in which ICs of transistors are defined as design parameters and optimized as well as the electrical performances. FOMs of analog and RF circuits were defined as the function of IC and the most efficient IC values were determined. Based on this knowledge, three different circuits were optimized by using the developed tool and a conventional tool. Synthesis results indicated that the proposed approach considerably accelerates the synthesis process, where the convergence time was improved by 25% similar to 30%.