This paper demonstrates implementation of some CDMA system compatible antenna array algorithms namely LMS and space code correlator (SCC) on an FPGA. A comparative study of FPGA and DSP implementation issues such as architecture complexity and weight vector computation time is also given. The implementations of the algorithms are performed on Xilinx Virtex 11 Pro FPGA and Texas Instruments (TI) TMS320C67x floating-point DSP platforms. For the signal modeling, cdma2000 reverse link signal model is considered for uniform linear array topology and varying multipath propagation conditions. Results show that the both algorithms, which were implemented on Xilinx XC2VP4 and TMS320C6713 DSP, provides weight vector computation time smaller than 10 ms period.