INTERNATIONAL JOURNAL OF ELECTRONICS, vol.96, pp.561-570, 2009 (SCI-Expanded)
The main purpose of this study is to investigate the so-called threshold inverter quantisation (TIQ) technique from a MOS transistor mismatch point of view. The logic threshold voltage values on the voltage transfer characteristics of three different area-sized CMOS cascaded inverters located on four different locations around a TIQ-based 5b Flash ADC are measured over 40 fabricated samples in a 0.5 m CMOS process to investigate the intra-die and inter-die mismatch effects. Based on the test results, the worst case inter-die and intra-die standard deviations occur (as 70 mV and 80 mV, respectively) when (Wn/Wp) has the minimum design value of (Wn/Wp=3.6 m/23.6 m). If the mean value of percent-standard deviations are chosen as the comparison parameter, then the comparator having minimum size of transistors exhibits the worst case matching property for having 2.91% of mean percent-standard deviation value for the intra-die case. This work concludes that the suggested resolution values for TIQ-based Flash ADC designs are to be less than 6-bit for 0.5 m CMOS process. However, it might be lesser for a smaller feature-size CMOS TIQ-based flash ADC design due to the expected increase in short channel and narrow width effects. On the other hand, if a higher resolution is preferred, then the channel length value should not be reduced to the minimum value that the related technology allows during the design process. In this situation, however, the sampling rate will be degraded.