Akademik Veri Yönetim Sistemi
ELECO 2021, Bursa, Türkiye, 25 Kasım 2021
This paper presents design of a 6-bit two channel time interleaved (TI) ADC in TSMC 180nm CMOS technology. TIQ based flash ADC cores are used in both TI channels. In this design, speed performance and low power properties are focused design goals. For this purpose, standart CMOS logic gates are preferred as much as possible together with the so-called TIQ comparator structure, which is also a CMOS logic for the analog part of the flash ADC cores. Aspect ratios of the MOS transistors used in the design are chosen carefully to be able to achieve high performance goals as much as possible. The main contribution of this study is to employ the TIQ technique for the second time in TI ADC architectures. The first time usage was also realized by the same authors and presented in ELECO 2018 conference. However, resolution is now increased to 6-bit and more professional design tool is used. Moreover, important design updates became necessary in some of the design blocks. According to simulation results, the proposed TI ADC has the sampling rate of 8 Gs/s. The simulation results also include +0.29 / -0.48 LSB of INL and +0.181 / -0.222 LSB of DNL values. Here, DNL and INL measurements are necessarily taken under transient analysis conditions instead of DC simulation conditions due to time interleaved nature of the ADC. 1Ms/s sampling rate and 1kHz input signal is choosen to obtain the linearity measures. While the power consumption of a single flash ADC core at 4Gs/s is 69.82 mW, the power consumption of the complete TI ADC is 176 mW at 8Gs/s sampling rate. The physical layout design of the complete ADC has currently been under construction. The post layout simulation and fabrication of the proposed ADC are projected future works of this study since it is already a financially supported academic research project.