IEEE 16th Signal Processing and Communications Applications Conference, Aydın, Türkiye, 20 - 22 Nisan 2008, ss.581-582
In this work a novel hardware proposed for Constrained 1-bit Transform based motion estimation to facilitate real time operation. The designed system occupies a small area in a general purpose FPGA fabric and it is therefore efficient to implement a whole video coding architecture on a single FPGA chip. The designed system can perform AM operation for a 2048 x 1152 pixel sized image frame at a speed of 20 frames/second.