In this work a novel FPGA based hardware is proposed to implement the Constrained One-Bit Transform based block motion estimation algorithm to facilitate real time operation. The designed system occupies a small area in a general purpose FPGA fabric and, that is why it is efficient to implement a whole video coding architecture on a single ASIC chip or an FPGA. The designed system can perform the motion estimation task for a 352x288 pixel sized image frame at a speed of 50 frames/second. The designed hardware can further be multiplexed to increase the parallelism for a real time operation for higher image frame sizes, e.g. for HDTV applications.